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GlobalFoundries prepares Tri-Gate competitor

GlobalFoundries prepares Tri-Gate competitor

Global Foundries invited us to its Dresden fab for the briefing.

In a recent briefing, Global Foundries revealed to bit-tech that it's already working on a competitor to Intel's recently-announced 3D Tri-Gate transistors.

When asked whether GlobalFoundries was developing a similar product to Intel's new 3D transistors, the company's VP of technology and integration engineering, Dirk Wristers, stated that the company did have ‘3D activity.’

In addition to this, Wristers also took the opportunity to flesh out GlobalFoundries' production process roadmap. As reported previously, the firm will use the gate-first method of semiconductor production at the 28nm node, but will move to gate-last production for its 20nm process in 2013.

In case you're unfamiliar with the latest CPU manufacturing jargon, gate-last and gate-first refer to the point at which a transistor's gate is put onto a CPU-production wafer.

Previously, CPU transistors featured a silicon gate and a silicon dioxide insulator. However, in order to combat the problems with current leakage as silicon gets thinner, most fabrication firms have now replaced the silicon-based parts with a metal gate and a high-k insulator made from a material such as Hafnium. This means that a fabrication company has to choose whether the metal gate electrode is dropped onto the wafer before or after the high-temperature heating process.

When pushed about the yield implications of gate-first production, Wristers stated that ‘gate-first is the right option [for Global Foundries], and is not an issue at this point.

He also stated that gate-first production saves around 10-20 per cent space at the 28nm node over the gate-last process used by both Intel and TSMC. According to Wristers, this enables ‘gate-first to offer superior value to gate-last.'

Despite being bullish on the use of the gate-first production, though, Wristers claimed that GlobalFoundries' 20nm gate-last production process should enable a 50 per cent reduction in the size of SRAM and logic circuits, when compared to 28nm production, and that the company had needed to innovate in its approach to 20nm production. This was forced, he explained, by the fact that the ‘density and scaling benefits of gate-first high-K metal gate no longer apply because of patterning-dominated lithography restrictions.

In addition to this, Wristers also confirmed that GlobalFoundries' R&D into 14nm transistors is ‘well underway’. Wristers confirmed that Global Foundries is exploring a number of novel approaches to this production node, including such as a Multi-gate FinFET transistor structure and a number of source mask optimisations to improve pattern fidelity.

Are you excited by the steady march of semiconductor production technology? How small can we make silicon transistors before they become unmanageable? Let us know your thoughts in the forums.

14 Comments

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r3loaded 12th July 2011, 13:05 Quote
" How small can we make silicon transistors before they become unmanageable?"
Well, that's an easy one to answer - the lower bound is going to be the size of silicon atoms themselves :)
Jezcentral 12th July 2011, 13:16 Quote
So, are we on course for Moore's Law to break down in 2017?
Xir 12th July 2011, 14:17 Quote
wouldn't happen to have mentioned something like "Triple-Spacer" or "Finfet" now would he?
WildThing 12th July 2011, 14:21 Quote
Nice to see Intel's competition doing something, and thanks Paul for the gate-first vs gate-last explanation, been wanting to read up on that for a while now. Cheers.
azazel1024 12th July 2011, 15:16 Quote
Last I heard the issues are around 8-10nm and that is about where any current and most theoretical manufacturing techniques are unable to produce a viable transister. So we have at least another 4-6 years before we are at neeing a major "break through" to keep advancing transister size.

The gist I got from the article is basically that "Hi, we are 1-2 years behind Intel, but don't worry, that works for us!"

Most of the time I hear things about using "backwards" technology because you haven't innovated or there is a defect, companies always spin it as a "design feature" or "it gives us X benifit". So 10-20% space savings compared to gate last at 28nm, I doubt that, or if true it is because of your manufacturing technique and the way you are laying out the chips. That or it may be true, but yields are significantly lower for you to change or too much time redesigning the process. Or it may also be true, but transistor performance is lower.

Since Intel and TSMC are doing gate last I don't think they decided to do that for no reason.
Bindibadgi 12th July 2011, 16:10 Quote
Thanks for the write-up Paul!
John_T 12th July 2011, 17:48 Quote
I love reading all this kind of stuff, even though I'll admit to only understanding about half of it!

I am amazed by the constant shrinking process, even more so when I look back at some of the older PC's I've had over the years. The original Pentium was, I believe, based on an 800nm technology - so to now have 28nm, to be preparing 20nm - and to be talking about 14nm transistors being well underway, I do think it's all pretty amazing.

Just roll out a tape measure to 800mm, then roll it back down to 20mm & 14mm for a visual comparison of scale. It's astonishing what they have been able to achieve in such a short space of time really...
ssj12 13th July 2011, 03:55 Quote
Why is it I suspect they saw Intel's tech announcement and said "oh crap, get to the drawing board ASAP!?"
Bindibadgi 13th July 2011, 07:06 Quote
Quote:
Originally Posted by ssj12
Why is it I suspect they saw Intel's tech announcement and said "oh crap, get to the drawing board ASAP!?"

FinFETs (branded 3D transistors) were originally developed by IBM actually iirc - who GloFo is in a co-operative development relationship.

It was on Ee times I think.

http://en.wikipedia.org/wiki/Multigate_device
Xir 13th July 2011, 12:33 Quote
Quote:
Originally Posted by Bindibadgi
FinFETs (branded 3D transistors) were originally developed by IBM actually iirc - who GloFo is in a co-operative development relationship.

It was on Ee times I think.

http://en.wikipedia.org/wiki/Multigate_device

Yup. The AMD-IBM alliance (direct follower of the AMD-Motorola alliance) :D
stonedsurd 13th July 2011, 12:37 Quote
That's more along the lines of what I'd like to see around here. Great article and well done Bit!

PS: Paul, do have an aunt named Holly?
ssj12 13th July 2011, 22:49 Quote
Quote:
Originally Posted by Xir
Quote:
Originally Posted by Bindibadgi
FinFETs (branded 3D transistors) were originally developed by IBM actually iirc - who GloFo is in a co-operative development relationship.

It was on Ee times I think.

http://en.wikipedia.org/wiki/Multigate_device

Yup. The AMD-IBM alliance (direct follower of the AMD-Motorola alliance) :D

That sounds like a horrid alliance. Thank god I have my Droid X2.
Xir 15th July 2011, 10:04 Quote
The AMD-Motorola Alliance gave you copper-interconnects which led to the break of the 1Ghz barrier.
(while Intel still said...naah Aluminum will do just fine)
saneblane 19th July 2011, 01:14 Quote
intel may be ahead in lithography but IBM is always ahead in R&D, that company just knows how to conduct themselves. and what they develop is the research they do benefit so many companies and people. amd then their is AMD, the company with the most pioneering chip designs, with the bulldozer arch, we don't even know how to count the cores. this is what happens when competitions is tough, people innovate
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