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Micron's Hybrid Memory Cubes win tech award

Micron's Hybrid Memory Cubes win tech award

Micron's future memory chips could well be using Hybrid Memory Cube technology, boasting vastly improved performance.

Memory specialist Micron has won an award for its Hybrid Memory Cube technology, a prototype system which promises to boost massively improve DRAM performance while dropping the power draw drastically over current generation hardware.

Based on through-silicon via technology - vertical conduits that allow components to be connected in a three dimensional mesh, in a way not dissimilar to Intel's tri-gate transistor technology - Micron's Hybrid Memory Cubes promise significantly improved performance over existing two-dimensional memory structures: current prototypes push 128GB/s, compared to peak throughput of around 12.8GB/s obtainable via commercial DDR3 DRAM implementations.

Micron's HMC isn't just about improving performance, however: prototype implementations of the technology boast a 70 per cent reduction in power draw during data transfer while reducing the footprint to one-tenth that of traditional two-dimensional memory; as a result, the technology is turning heads in the world of ultra-mobile computing and embedded systems.

Sadly, the technology isn't destined for desktops and smartphones just yet: due to the heightened cost of HMC chips compared to traditional DRAM, the company is concentrating its efforts in large-scale networking and high-performance computing (HPC) markets. Once production costs have lowered, industrial automation will be next before the consumer markets finally get their hands on the technology.

That somewhat lengthy roadmap to affordable implementations hasn't stopped The Linley Group, a microprocessor and semiconductor industry analysis organisation, awarding the company Best New Technology in its 2011 awards. 'Hybrid Memory Cubes promise greater density, lower latency, higher bandwidth, and better power efficiency per bit compared with conventional memories,' explained Tom R. Halfhill, a senior analyst at The Linley Group and one of those responsible for the award. 'Early benchmarks show a memory cube blasting data 12 times faster than DDR3-1333 SDRAM while using only about 10 percent of the power.'

'With so many other great innovations out there, we're especially honored to receive this prestigious award from The Linley Group. This world-class recognition is a reflection on the team that is working to match processors with memory and break down the memory wall by bringing the Hybrid Memory Cube to the market," added Brian Shirley, vice president for Micron’s DRAM Solutions Group, at the award ceremony. 'Special thanks to the Micron engineers who've designed this breakthrough architecture, and to our esteemed colleagues in the industry who are helping to expedite the specifications and manufacturing for this revolutionary technology.'

Wondering what chips will be turned three-dimensional next, or just impatient to get your hands on consumer-grade implementations? Share your thoughts over in the forums.

8 Comments

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azazel1024 27th January 2012, 16:12 Quote
This doesn't sound remotely like FINFET technology (Intel's trigate transisters). One is a 3 dimensional interconnect instead of being planar (2d interconnect). This is actual interconnects BETWEEN transitors, not within the transistor itself (which is what FINFET is all about).
Gareth Halfacree 27th January 2012, 16:29 Quote
Quote:
Originally Posted by azazel1024
This doesn't sound remotely like FINFET technology (Intel's trigate transisters). One is a 3 dimensional interconnect instead of being planar (2d interconnect). This is actual interconnects BETWEEN transitors, not within the transistor itself (which is what FINFET is all about).
Which is why I said it was "not dissimilar," rather than "exactly the same." Both are about extending things which are usually two dimensional into the third dimension.
ffjason 28th January 2012, 15:02 Quote
lol @azazel1024 - you been told!!
ch424 28th January 2012, 16:08 Quote
azazel1024 is correct though, tri-gate transistors and stacked dies do have very little in common.
Bakes 29th January 2012, 11:57 Quote
Quote:
Originally Posted by Gareth Halfacree
Quote:
Originally Posted by azazel1024
This doesn't sound remotely like FINFET technology (Intel's trigate transisters). One is a 3 dimensional interconnect instead of being planar (2d interconnect). This is actual interconnects BETWEEN transitors, not within the transistor itself (which is what FINFET is all about).
Which is why I said it was "not dissimilar," rather than "exactly the same." Both are about extending things which are usually two dimensional into the third dimension.

That is the only way in which they are similar, though. By the very same logic, you could add 3D printing to the list. In fact, it seems as though 3D printing is actually a superior analogy to use!
Gareth Halfacree 30th January 2012, 08:09 Quote
Quote:
Originally Posted by Bakes
That is the only way in which they are similar, though. By the very same logic, you could add 3D printing to the list. In fact, it seems as though 3D printing is actually a superior analogy to use!
Sure, that's a superior analogy - if you ignore the fact that it's about improving computing power and performance by extending things which are traditionally two dimensional (either the transistors themselves in tri-gate or arrays of transistors in HMC) into the third dimension. Then 3D printing is a pretty poor analogy, wouldn't you say?
Bakes 30th January 2012, 11:07 Quote
Quote:
Originally Posted by Gareth Halfacree
Sure, that's a superior analogy - if you ignore the fact that it's about improving computing power and performance by extending things which are traditionally two dimensional (either the transistors themselves in tri-gate or arrays of transistors in HMC) into the third dimension. Then 3D printing is a pretty poor analogy, wouldn't you say?

Not particularly. There have been many attempts to improve computing power by integrating 2d packages into 3d.

The Apple processors for example have several dies inside, mounted atop each other, in order to reduce space - using what I can only assume is a similar method (might not be, but the article is unclear).
http://guide-images.ifixit.net/igi/yEfJohqHnWinU1vx.medium

With 3D printing, layers are often printed atop each other, with chemical bonds joining the layers together, improving the process.

If you consider your exact wording,
Quote:
vertical conduits that allow components to be connected in a three dimensional mesh, in a way not dissimilar to Intel's tri-gate transistor technology

you can see that your comparison is not correct, with the technologies being different. Tri-gate transistors are three dimensional, sure, but I fail to see the vertical conduits linking layers of silicon you speak of in their production process.
Gareth Halfacree 30th January 2012, 11:11 Quote
Quote:
Originally Posted by Bakes
If you consider your exact wording, [...] you can see that your comparison is not correct, with the technologies being different.
Okay, my wording was unclear: I didn't meant to infer that tri-gate uses TSV (although I can see how it reads that way,) but simply that tri-gate is another example of 2D-to-3D in chipmaking. In retrospect, it'd have been much clearer as a separate sentence: "Another example of chipmakers taking a 2D technology and expanding it to the third dimension is..."
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