TSMC announces 5nm, 3nm fab plan

December 9, 2016 // 11:51 a.m.

Tags: #10nm #3nm #5nm #elizabeth-sun #fab #fabrication #feature-size #intel #process-node #semiconductor #taiwan-semiconductor #tsmc

Chip fabrication giant Taiwan Semiconductor (TSMC) has announced plans to build a new £12.5 billion facility to produce parts on 5nm and 3nm process nodes.

Anyone with an interest in computing will be familiar with Moore's Law, the observation by Intel co-founder Gordon Moore that the number of transistors within an integrated circuit have a tendency to double every eighteen months. Originally positioned as a historical observation, Moore's Law has become exactly that: a concrete law that the industry feels it must follow or risk being left behind. Increasing the number of transistors in a chip without ending up back at room-sized computers is only possible, of course, by making those transistors ever smaller, creating parts at ever decreasing feature sizes.

As these feature sizes decrease, the difficulty in making a working part increases thanks to various issues ranging from current leakage to bizarre quantum effects. Intel recently further delayed its own 10nm node thanks to these problems, but TSMC is confident it will be able to begin production of even smaller nodes in the future - so much so, in fact, it's building a new £12.5 billion fabrication facility targeting 5nm and below.

'We're asking the government to help us find a plot that is large enough and has convenient access,' TSMC's Elizabeth Sun told local news outlet Nikkei Asian Review this week, 'so we can build an advanced chip plant to manufacture 5-nanometer and 3nm chips.'

The facility, the company claims, will require 50-80 hectares of land, and thus far TSMC has not provided a timescale either for the facility's completion nor its expected roadmap to 5nm and below, which it had claimed in 2012 would occur by 2020. It has, however, promised to launch its first mass-produced 10nm chips in early 2017.
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