bit-tech.net

Micron announces performance-boosted DDR3

Micron announces performance-boosted DDR3

Micron's latest DDR3 modules, created in partnership with Broadcom, promise an 18 per cent boost in operations per second over the previous generation equivalent.

Memory specialist Micron claims to have solved the four-bank activation window timing challenge in dynamic RAM (DRAM) with an immediate 18 per cent boost in performance for DDR3-2133 modules.

The four-bank activation window (tFAW) is one of a number of timing parameters in modern double-data rate (DDR) DRAM which, the company claims, can restrict performance in high-bandwidth environments. Typically, this value is set to 35ns - meaning that to activate ten banks takes three tFAW cycles, or 105ns.

The delay in bank activation causes a performance bottleneck problem in high-performance, high operations per second (OPS) scenarios, particularly in the network industry where data must be shuffled to and from RAM extremely quickly to keep up with the ever-increasing speed of network connections. As a result, Micron has worked with Broadcom to develop DRAM modules with a significantly reduced tFAW cycle of just 30ns.

According to the pair's testing, the new modules offer an improvement in operations per second of 18 per cent - a not-insignificant gain in OPS-hungry devices. The first such device to feature Micron's new high-speed tFAW DRAM modules will be Broadcom's BCM88030 network processing unit (NPU) with a claimed 200Gb/s wire-speed layer two, IPv4 and IPv6 lookup capability.

'OEMs today continue to tackle the challenge of an ever-increasing volume, velocity and variety of data,' claimed Robert Feurle, vice president of DRAM marketing at Micron, at the announcement. 'We are delighted to be working with Broadcom to validate a solution that helps alleviate the throughput challenge for our mutual customers.'

Although the modules have been developed in partnership with Broadcom, Micron is offering the parts to all customers in 2GB and 4GB modules. Initially, the target market will be OPS-heavy network processing devices, but we can expect to see the technology coming to more consumer-facing devices in the near future as well.

10 Comments

Discuss in the forums Reply
exceededgoku 18th December 2013, 12:07 Quote
so we have 105ns for current implementatios and this brings that down to 90ns...

Is that really solved, or mitigated?

In my eyes a solution would be 30ns for the whole operation.
Anfield 18th December 2013, 12:39 Quote
Initially it won't be available in consumer products.
In 2014 Cpus will start to support DDR4.

So will we ever really get any benefit from this expected at some point in the future improvement for DDR3?
SAimNE 18th December 2013, 12:49 Quote
Quote:
Originally Posted by Anfield
Initially it won't be available in consumer products.
In 2014 Cpus will start to support DDR4.

So will we ever really get any benefit from this expected at some point in the future improvement for DDR3?
anyone who's planning on running kaveri will welcome this improvement.... tho i cant imagine they wouldnt want to wait until ddr4 arrives.
Gareth Halfacree 18th December 2013, 13:51 Quote
Quote:
Originally Posted by exceededgoku
In my eyes a solution would be 30ns for the whole operation.
And 0ns would be even better. Impossible, but better. Micron isn't saying it's got rid of tFAW - that's not possible with DDR, it's part of the way it works; what Micron is saying is that it has solved a timing challenge which has previously prevented it, and other DRAM makers, from reducing the tFAW window.
Quote:
Originally Posted by Anfield
In 2014 Cpus will start to support DDR4. So will we ever really get any benefit from this expected at some point in the future improvement for DDR3?
The same improvement can be used with DDR4, and DDR5, and DDR6... Basically, tFAW is common to all DRAM. Improving the tFAW cycle means improving all DDR, whether it's the original DDR standard or next-next-next-generation DDR6. It just so happens that Micron is only producing DDR3 using the faster tFAW cycle at present, 'cos that's all its customers want. Should Broadcom's next NPU want DDR4, then Micron will make DDR4 with the same reduced-length tFAW cycle.
exceededgoku 18th December 2013, 14:23 Quote
Thanks for the post Gareth, good news then I guess :).
azazel1024 18th December 2013, 14:41 Quote
A key point here is that for networking gear and servers, this isn't simply an improvement in possible bandwidth/through put, this is a reduction in latency, which is a good thing.

I can also see how it could be of benefit to regular consumer computing too, though at least from what I have seen of various tests, there aren't a whole lot of operations that are particularly latency dependent in the consumer sphere. I would think something like iGPUs this could benefit a lot, though there it seems more bandwidth than latency sensitive too.
Cthippo 18th December 2013, 14:55 Quote
What is that character before the F in FAW?
Gareth Halfacree 18th December 2013, 15:25 Quote
Quote:
Originally Posted by Cthippo
What is that character before the F in FAW?
An italicised, superscript lower-case t: t. Used to signify time as a variable.
play_boy_2000 18th December 2013, 16:29 Quote
The Broadcom's BCM88030 was announced ages ago... is this just a latency reduction for the chip?
Gareth Halfacree 18th December 2013, 16:39 Quote
Quote:
Originally Posted by play_boy_2000
The Broadcom's BCM88030 was announced ages ago... is this just a latency reduction for the chip?
This is a latency reduction in Micron's DDR3 modules, at Broadcom's request and for use with the BCM88030 and other NPUs.
Log in

You are not logged in, please login with your forum account below. If you don't already have an account please register to start contributing.



Discuss in the forums