Toshiba outs high-performance STT-MRAM technology

December 11, 2012 // 11:28 a.m.

Tags: #cache #cache-memory #magnetoresistive #memory #mram #spin-transfer-torque #sram #static-ram #stt-mram #toshiba

Toshiba has announced a prototype version of a spin-transfer torque magnetoresistive memory element, the first step on the road to commercialising STT-MRAM as a replacement for static RAM (SRAM) cache.

Based, as the name suggests, on magnetic rather than electronic storage, magnetoresistive memory has a couple of major advantages over existing SRAM: firstly, it doesn't suffer from the same current leakage issues at smaller process sizes, and secondly it's non-volatile - meaning it doesn't require the constant input of power to keep its data intact. For computers, which are constantly packing more components into less space and requiring greater performance from the same power and thermal envelopes, those are two very tempting propositions.

Sadly, MRAM has proven difficult to commercialise: although its origins can be found in the core memory of the 1950s, modern MRAM has been one of those it's-just-around-the-corner technologies for years. Commercially viable products, including a 16Mb part launched by Infineon in 2004 and NEC launching a high-speed drop-in SRAM-compatible version in 2007. Thus far, however, the technology has remained a niche product, with radiation-hardened versions finding some traction in defence and aerospace industries but making little impact elsewhere.

Spin-transfer torque technology, first considered for use with MRAM devices in 2007, promises to solve one of the major barriers: the power required to flip the magnetic polarisation in MRAM devices. Although MRAM requires no power to retain its data, actually programming the data into the device previously required vast quantities of energy with localised heating proving the most popular method. Spin-transfer torque, by contrast, uses a spin-polarised electrical current to flip the orientation of the magnetic layer - using significantly less power than other methods in the process.

It was good enough for lab use - Qualcomm demonstrated a 1Mb STT-MRAM device in 2011 - but issues still surrounded the technology, largely a trade-off problem where manufacturers had to pick between SRAM-like performance or low power draw. These issues, Toshiba claims, are now solved through the use of perpendicular magnetisation. Replacing existing in-plane magnetisation methods, perpendicularly magnetised MRAM requires significantly less current and can use much smaller transistor sizes.

It's not a new concept: Toshiba announced the first perpendicular MRAM devcie in 2007. The company's latest announcement, however, puts the technology a significant step closer to commercialisation: it's the first time MRAM elements have been produced at a process size below 30nm, and the first time the power draw for writing has come close to beating traditional SRAM with a reduction of around 90 per cent compared to in-plane MRAM.

Performance of the new MRAM modules has been confirmed under simulation, in which the simulated device - a smartphone processor carrying out standard operating functions - dropped average power draw by two-thirds compared to the same chip operating with traditional SRAM.

Sadly, Toshiba is quiet on one thing: when it hopes to bring the STT-MRAM devices to market. Far from offering a time scale, the company has stated only that it 'expects to bring the new memory element to STT-MRAM cache memory for mobile processors integrated into smartphones and tablet PCs, and will promote accelerated research and development toward that end.'