If this CPU-Z screenshot is to be believed, then AMD's Athlon II "Rana" CPUs will have no Level 3 cache.
Further reports have now appeared about AMD’s potentially forthcoming Athlon II processor, as German tech site Hardware-Infos
(Google translation here
) claims to have sourced a CPU-Z screenshot from an Athlon II machine from a motherboard manufacturer.
As previous rumours
about the Athlon II suggested, the CPU-Z 1.50 screenshot implies that the CPU uses AMD’s new Rana core, which looks like it might be a radically different beast from AMD’s current Deneb core used in its Phenom II desktop CPUs. For a start, there’s no Level 3 cache. Instead, the Athlon II X3 405e shown in the screenshot has three 512KB blocks of Level 2 cache (one for each core), along with three 64KB blocks of Level 1 Data cache, and a further three 64KB blocks of Level 1 Instruction cache.
This means that there’s no pool of shared cache between the CPU cores, which is a similar cache architecture to the system used in AMD’s dual-core K8 architecture, in which each core also had its own block of Level 2 cache. The main difference between this and K8, of course, is that this architecture can feature three or four cores, rather than just two.
Although the Rana core appears to be built on the same 45nm process as AMD’s current Deneb core, Hardware-Infos claims that it’s been told that the triple-core CPU will consume just 45W. The 2.3GHz chip has a core voltage of 1.2V, and the lack of Level 3 cache would enable AMD to make a significantly smaller die, as well as reducing the power consumption. Similarly, AMD claims that its recently-announced quad-core Opteron EE
consumes only 40W, so this isn’t out of the realms of possibility.
The site also has another screenshot of a quad-core Rana processor, which is otherwise identical in terms of specifications. This CPU is detected as a Phenom II by CPU-Z 1.50, but CPU-Z is often understandably inaccurate when it comes to pre-release CPU architectures.
Of course, all of this news is still very much at the rumour stage yet, and none of this has been confirmed by AMD. That said, a low-power multi-core architecture could prove to be popular in media PCs and small form factor PCs. Would it make sense for AMD to remove the Level 3 cache to create a low-power, budget CPU? Let us know your thoughts in the forums