Medicore clock speeds and high CAS, but still with plenty of bandwidth to spare, it seems...
Instead of just a quick news piece this has turned into a bit more of an in depth discussion about what we expect to happen with Nehalem/Bloomfield and the memory market when it arrives very soon. We've known for a little while that Nehalem's memory will only run at 800MHz or 1,066MHz opposed to the usual 1,600MHz+ that we have now, but the usual motherboard manufacturers are working on a "1,333MHz OC" option which most of them already have running fine (so we hear).
The problem is people might perceive this as slow and it will cause a bit of a pickle for memory vendors who rely on performance margins for marketing material.
DDR3 memory today will easily work at 1,333MHz speeds, but the news through the grapevine is that Intel is going for a low power emphasis so overclocking the memory will be harder. In fact, from quite a few sources in Taiwan, we've heard that Intel is more than happy with CAS-9 at 1,066MHz which is slow.
It's been strongly suggested by others that Nehalem's memory voltage will be directly linked and possibly the same as the CPU voltage - limiting the amount of beans you can force through your memory, however we're almost certain this is not the case. You'll be limited by how much memory controller (aka northbridge) voltage you can use and this will be tied to the CPU voltage at a particular ratio as the memory controller and CPU voltage planes are different. This is evident by Intel's admission already. If the P45 northbridge is anything to go by, you don't need that much extra voltage anyway so the vast majority of us will be OK, however the most extreme overclockers might cry foul.
Like we've already shown in our early looks, the actual memory voltage on X58 boards is controlled by two or three phases on the motherboard - so actual DDR3 voltage will be independent. You'll be limited by what memory multipliers you can run, but that's not different than what's currently available on Intel platforms and keeping everything tied into a small number of variations means the internal latency is minimised.
So while we'll be not hitting super high memory frequencies, we should be able to hit low CAS numbers from performance memory instead - CAS-5 at 1,333MHz will do nicely, thanks. It'll be back to the days of DDR where there was not much overhead left and memory was sold on its low CAS as much as its capability to do super high clocks. This is on the proviso that Intel's integrated northbridge mimics the way P45/X48 can easily achieve low latency numbers, whereas in contrast Nvidia' nForce 790i Ultra SLI prefers a high clock and high latency design. We've already found DDR3 at 1,600MHz and CAS-6 gives almost the same memory efficiency as 2000MHz at CAS-9.
Also, since Nehalem has cut out the archaic, latency heavy front side bus for a direct connect approach like AMD, we've heard from industry insiders that triple channel DDR3 will hit "14,000MB/s easily in Everest" (which is typically single core loading software). Intel also showed off Nehalem setups executing 22GB/s of bandwidth at IDF for "STREAM triad multi-threaded" tests, which is basically a more "real world" approach that factors in read, write and modify data to memory. We've no idea of what latencies and speeds the memory was running, however since 1,333MHz OC has only been QA'd recently in Taiwan, we'd hazard a guess these numbers represent the standard 1,066MHz variety.
Our guess is to look out for memory vendors advertising 3GB and 6GB triple-channel kits in the next month or so sporting ever lower CAS numbers rather than high clocks. This is how we expect them to try and make their margins for premium kits. It will be interesting to see how extreme cooling the CPU can affect the memory controller ability too, or if the complex eight layer PCB and triple channel DDR3 is the limiting factor - motherboard design might play a key factor as much as BIOS development in the forthcoming months.
The memory controller is unlikely to change between Bloomfield and Lynnefield/Havendale and with Lynnefield and Havendale, we're not going to have triple channel memory to make up the numbers - dual channel DDR3-1066 sounds slow
but Intel are not going to let its mainstream CPUs out perform its Bloomfields that will charge the margin for "enthusiasts" - will it just have one channel disabled? Can you turn it on in future CPUs? The memory controller may not even change with future core revisions of Bloomfield, unless there are so many cries from hardcore overclockers and performance enthusiasts, but we expect controller changes allowing faster memory will require new board qualifications and PCB testing - Intel likes to make sure everything works solidly first and foremost.
Considering how intimately the power regulation features are tied to all components of a new CPU, we can't see this as a viable task either. Couple into the fact that the performance sector is tiny, it's unlikely that the cost and time: marketing benefit and revenue ratio will be in our favour. If AMD had something to challenge the performance crown there would be far more of an incentive, however we can't see that happening even with Shanghai. So this looks like the status quo for a while yet, so once new memory kit prices level out expect it to be an investment that should last a while.
Are you waiting for triple-channel kits of DDR3 specially designed for Nehalem? Let us know in the forums