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Intel to add to CPU lineup in 4Q07
Author: Brett ThomasPublished: 15th June 2007
"Going to play in the fields" - Intel is bringing another processor to the table with the new Yorkfield core.
First, we'll hit the un-exciting part. Intel has added an E4600 to the list, bumping up the Allendale line to a feisty 2.4GHz. The chip will remain on an 800MHz Front Side Bus, so we're mostly seeing the culmination of processing refinement. Now that things are in full swing and processing methods have matured, the Allendale core has been able to get a bit of a speed bump by increasing the multiplier. However, that is the only change from other members of the E4000 series.
What has been grabbing peoples' attention, however, is the new "Yorkfield" core. Yorkfield is the follow-up to Kentsfield, and will be the new base of Intel's "Extreme" lineup. The new chip will sport the same 1333MHz FSB that the Kentsfield-based Extreme processors already do, with two major changes - the chip will be made on a 45nm process and will have 12MB of L2 cache.
The die shrink will come with the usual benefits of reduced temperatures and increased efficiency, but it is losing something in the process. Intel has scrapped its TXT technology in the Yorkfield redesign, which was meant to encrypt all running processes. The concept of hardware-level encryption would mean viruses could have a harder time inserting themselves into proper parts of already running threads.
Whether this loss will truly be a detriment to the system is unknown, as the technology is so new as to not really have illustrated whether it has any effect in the first place. Intel doesn't really explain why the TXT technology didn't make it into the new cores -- it could be anything from having problems incorporating it with the die shrink to the realisation that the cost vs. benefit was just not there. Of course, one has to wonder if there really is a need for Intel to be inserting itself into the security field to begin with, so maybe the drop-off is best for everyone involved.
Have you got a thought on the new processors? How about the quiet drop-off of TXT technology? Tell us your thoughts in our forums.
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Also, i think Bit-tech should start using this image for Intel stuff:
http://farm1.static.flickr.com/71/218760786_aebe597036_o_d.png
Blasphemy.
Kentsfield isn't exactly native quad-core as its 2 Conroe dies in one CPU package, as opposed to 4-cores on one die like Barcelona is going to be. Yorkfield will just be a shrink on Kentsfield so it will have the same 2 die approach.
I'm surprised though, Intel have had quad cores around for quite a while, i would have thought they could get it onto 1 die by now
also, zomg 12mb L2 cache :o :o how long before you don't need ram anymore
i have to agree - intel should have a native quad core by now, or at least they should be well on their way to one. id rather have a native 65nm quad core than a 45nm kentsfield...
and yes, that cache is massive... but its still not 2gb ram :p
cores 0 and 1, and 2 and 3 can communicate through their caches so its only when two cores from seperate dies have to communicate a unified design would have performed better. Such occurances are few and far between.
So you can either have a native quad core that will be expensive to produce, made in limited quantities (thus even more expensive), and with less binning options (if it works at all it will get used as a quad) - or a MCM that give far higher yields, performs the same in 99.9% of all situations to a native quad solution, is priced cheaper and can be made from cherry picked cores (if all dies are dual cores then far higher quantities make it into individual bins be it for high frequency, low power consumption or a combination of the two. Bins can then be chosen for use in either quad or dual core packaging options, for a more flexible product range).
Until there is a need for greater inter core communication the MCM solution is far better - and a mcm with direct communication (not via northbridge) would be the preferred intermediate step with all the advantages of a mcm, with a performance benefit over the current implementation. We will have this once CSI replaces the fsb, so we will have native quad cores and octo core mcms.
For AMD, hypertransport could have provided this now, so a mcm would have suited them even more than intel - pushing for a 'native' quad core was a huge screw up on their part. Had they not criticised intel so much for releasing a non native quad core (over a year before amd look to get their solution out), you could bet AMD would have MCM's out now, its only to save face that their persuing native designs first. I would expect a mcm (2x2core) product to be released within a year targetting home users (with the native quad aimed at server usage where the unified die would yield some benefits, and the increased costs could be recouped).
also native quad core does make a big difference in the server market (well SMP market) where people are actually using all 4 cores with heavy multi threading, but for the home user, your right, a lot of the time all 4 cores don't need to communicate (well except if your using windowz XP where processes are given equal times on each core, moving the program between each of the available cores, which you have to fix using affinity masks)
however, the link between those caches is another cache, running at the processor's speed, rather then going through the slow FSB
Afaik Intel has NOT dropped TXT. TXT is supposed to be an addition to Vpro and is thus aimed for the buisness sector, represented by the Wolfdale Dual-Core CPUs. Yorkfield, being the Quad-Core CPU, is supposed to be the CPU for hardware-enthusiasts, not for the buisness sector. One could argue that a highend CPU with the steepiest price should come with all the available features, on the other hand, if I understood Intel's whitepapers correctly, TXT needs a virtualized enviroment to function properly or at least a serious amount of code changes among OS kernel parameters. All recent improvements on virtualization aside, the whole virtualization thing is still in it's infant stages. Intel apparently, and in my opinion correctly, asumes that no "enthusiast", aka gamer, will get his hands on virtualization any time soon. The usual hardcore gamer installs a regular XP or Vista and doesnt use virtualization due to performance limitations, so Intel thinks.
Also afaik, all new "Exx50", "yet to be announced" Wolfdale CPUs, that currently is the E6550, the E6750 and the E6850 (there doesnt seem to be an E6650 atm, probably due to the higher FSB), WILL come with fully activated TXT. I, of course, can't say with an aboslute certainty, but let's say, I'm 99% sure ;-)
Concerning the "native / non-native" discussion: First of all, and forgive me for saying so, I am a bit of a lingustic freak here :D, I don't think "native" or "non-native" is the right choice of words. Wouldn't native mean, that someone or something is something "per sé"? That wouldn't apply for either AMDs Barcelona, because it can and also will come with also 2 cores and not necessarily with 4 cores, nor Intels Yorkfield, for obvious reasons. I think "monolithic" and "semi-monolithic" is the term to use here. In the end it really is just a matter of lingustic subtleties, i guess :D
The reason for Yorkfield "still" being a semi-monolithic CPU is quite simple: Money. Intel could produce Yorkfield as a monolithic CPU, but that would increase the overall production-cost in a not too small percentage. Intel, of course, has to test every core after the lithography, if one core or more doesnt work correctly, either one core has to be deactiveted or the hole unit has to be dismissed. If Intel would produce Yorkfield as an monotlithic CPU, the percentage of those units, that have to be dismissed due to one or more defective cores is apparently higher than that of a semi-monolithic CPU build out of two Dual Core dies. Why excatly is that deficiency quota higher this way and lower that way? I have no idea. Ask manufacturers like Intel or TSMC, but they probably won't tell you ;-)
My guess is, that the cache does the trick. When I look at the design of a modern CPU, I can't help myself but to think that the cache is the least error-tolerant part of the whole thing. In a monolithic CPU, all cores would share the same cache, with Yorkfield, that would mean one single cache with the enormous size of 12 MB. I don't find it hard to imagine that the size of the cache is not directly proportional to the difficulty of manufaturing it, maybe it's a quadratic propotion, say, if the size is doubled, that chance of actually getting the whole cache to work is one fourth, maybe it's some other exponential proportion, like I said, I don't know, I'm just guessing.
Until late 2006, it was still rumoured that Intel's 45nm production process had solved enough problems for a monolithic design to be the more cost-efficient one, but in early 2007 Intel confirmed other rumours, that Yorkfield would still be a semi-monolithic CPU.
I totally agree that a semi-monolithic quadcore is a "no buy", each two cores would have to communicate with the other two via an CPU-external bus, which would be the FSB in Intel's case. And that pretty much sucks, cause the FSB has already reached the end of most of it's capacity. Seems like we will have to wait for Nahelam...