The RISC-V open instruction set architecture (ISA) received a major boost this week with the news that storage giant Western Digital is to begin shipping a billion RISC-V cores in its products within the next two years.
Originally developed in 2010 at the University of California, Berkeley, RISC-V is, as the name implies, a reduced instruction set computing (RISC) instruction set architecture (ISA) designed to compete with the like of x86, Arm, and MIPS in everything from embedded computing to high-performance computing (HPC). Unlike its rivals, though, RISC-V is entirely open: Where developing an x86 processor requires an expensive licence, anyone is free to create a RISC-V chip without the need for royalty payments or permission thanks to the permissive BSD Licence under which RISC-V is published.
This open-source nature has given rise to a wealth of RISC-V projects around the globe, many of which have begun to bear fruit in the last couple of years. SiFive already has embedded-targeted implementations shipping and has recently released a microprocessor implementation capable of booting the Linux kernel, building on the upstreaming of a RISC-V port in the latest release, while the Shakti Processor Project is working on implementations which scale from energy-efficient microcontrollers to 'H-class' chips with up to 100 cores designed for supercomputing projects.
Western Digital, though, is the first mainstream company to announce a sea-change from proprietary ISAs to RISC-V. "In the world of computing there is big-data processing and fast-data processing. Conventional architectures are mostly general-purpose in nature; they do one thing well and the other not so well,' Western Digital chief technical officer Martin Fink told attendees of the RISC-V Workshop this week, held at WD's US campus. 'New-gen applications and workloads need to have the right type of processing at the right time and place in order to be efficient and fast. We're not going to make general-purpose systems on chips at WD. That's been done. Turns out that RISC-V does both fast data and big data very well on an HPC basis. That's where we're going.'
'Western Digital is a leader in storage products and technologies, and we are now expanding that leadership to open, data-centric compute architectures,' added Mike Cordano, president and chief operating officer at Western Digital. 'RISC-V will allow the entire industry to realise the benefits of next-generation architectures while also enabling us to create more purpose-built devices, platforms and storage systems for big data and fast data applications. We are moving beyond just storing data to now creating entire environments that will enable users to realise the value and possibilities of their data.'
The move marks the first time Western Digital will have launched a product not based on x86, Arm, or MIPS architectures or their derivatives, and the company is going big: Fink claims WD will ship a billion RISC-V cores within the next two years, which would make it the biggest RISC-V implementer by far. The work could scale, too: While the company has indicated its initial RISC-V products will be high-performance parts for enterprise data processing, the scalability of the ISA means that the company could potentially replace the proprietary cores in its consumer-centric storage products - right down to the controllers that power its hard drives and SSDs - with RISC-V equivalents.
November 6 2020 | 17:30