TSMC highlights 5nm and 3nm process at Technology Symposium

Written by Jennifer Allen

August 25, 2020 | 11:00

Tags: #3nm #5nm #7nm #n12e

Companies: #tsmc

TSMC began its 26th Technology Symposium event this week, beginning with details surrounding its 7nm N7 process, 5nm N5, N4 and 3nm N3 nodes. 

With the initial focus on the 5nm nodes set for release over the next couple of years, we learned a fair bit more about the N5 node. Currently in mass production, it makes use of EUV technology and promises up to a 30 percent improvement in power consumption or up to 15 percent superior performance over the company's current N7 node. There's also an expected 1.8x improvement in logic density.  

Alongside that is also TSMC's enhanced 5nm node known as N5P aimed at high performance applications. That one is expected to be in production in 2021 and will provide a 10 percent improvement in power consumption or a 5 percent increase in performance compared to the aforementioned N5 node. 

Demonstrating TSMC's forward thinking, there's also the existence of N3, the appropriately titled name for the company's 3nm node. That doesn't enter risk production until late 2021 so it's not expected to be in mass production until sometime in 2022. There's also the N4, TSMC's 4nm node, which enters risk production in late 2021 before hopefully moving into mass production by 2022. Given the long term plans here, it wasn't surprising when TSMC didn't release any details on performance improvements here. While plenty of figures were touted about 5nm and 3nm, we haven't got any information on what to expect from these two just yet.

It's a strong turnout for a company that's done an impressive job of becoming an industry leader over the years and currently means it's ahead of the competition. For instance, Intel only has plans for its 7nm node in late 2022 at the earliest - around the same time as TSMC aims to push its 3nm node into high volume production. 

Continuing new node news, TSMC also announced details surrounding its N12E process. This one is designed with low-power devices in mind like IoT gadgets, mobile and edge devices, so it may seem initially less exciting but could lead to some rather exciting innovations in the field. The node is expected to offer up to 76 percent improvement in logic density, along with 49 percent improvement in speed while also improving power consumption by 55 percent. 

Devices like wearables, smartwatches, and smart earbuds are set to benefit from this process with TSMC's thinking that it'll transform devices to have far improved AI, leading to a better experience and potential advantages like superior smart health monitoring on wearables. It should tie neatly into the growth of 5G too. 


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