MIT stings chip simulators with Hornet

March 2, 2012 | 12:49

Tags: #cpu #fpga #hornet #many-core #multi-core #processor #simulation

Companies: #massachusetts-institute-of-technology #mit

A team of researchers at the Massachusetts Institute of Technology have unveiled a software simulation system designed to help develop the next generation of many-core processors.

Dubbed Hornet, the system is designed to model the performance of multi-core processors much more accurately than existing tools. The result, the team claims, is a tool that will make it a lot easier to evaluate many-core processor designs before committing to a run of silicon.

When scaling a processor design to hundreds - or, in some cases, thousands - of cores, things get extremely complex. As a trade-off, previous modelling systems have sacrificed accuracy in the name of efficiency in software systems and depended on scale models built from field-programmable gate arrays (FPGAs) where more accurate simulations are required.

Myong Hyon Cho, PhD student at MIT's Department of Electrical Engineering and Computer Science, claims Hornet offers something to fans of either approach. 'We think that Hornet sits in the sweet spot between them.'

Unlike existing simulations, Hornet is claimed to be cycle-accurate even when dealing with a model of a 1,000-core chip. 'Cycle-accurate means the results are precise to the level of a single cycle,' explains Cho in a statement on Hornet's release. 'For example, it has the ability to say "this task takes 1,223,392 cycles to finish."'

That's something existing simulations simply can't offer, Cho claims. While good for evaluating the general performance of a given processor design, the sacrifices made in the name of performance and scalability mean edge-case problem scenarios can be missed.

Hornet, on the other hand, is significantly more likely to capture these rare exceptions and flag them before a design is committed to silicon. In research presented at the Fifth International Symposium on Networks-on-Chips, Cho and his team analysed a proposed multi-core computing technique in which the chip passes computational tasks to the cores storing the data required for said tasks, rather than wasting time transferring the data across to the cores chosen to perform the task.

It was a neat idea, but Hornet flagged a potential issue: deadlock. While unlikely, it was possible for a multi-core processor using the aforementioned technique to get itself in a situation where every core was locking resources required by another core - halting execution. It was something the other simulators had missed, but Hornet caught.

That demonstration was enough for the group to walk away with a Best Paper award, and it has chip design companies interested. While Hornet is, Cho admits, slower than a traditional simulator, it's fast enough that it would make a good intermediate step between rapid proof-of-concept simulation and FPGA prototyping.

As companies look to make the move from multi-core to many-core processors, technologies like Hornet are going to become increasingly important. Thus far, however, MIT has not announced whether any chipmakers have ponied up for a Hornet licence.
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