More details have emerged regarding AMD's Bulldozer successor Piledriver, but not from the chip maker itself. Rather, a partner company called Cyclos Semiconductor is claiming that the red team has chosen its resonant clock mesh technology for the next-generation processor family.
Making the announcement at the International Solid-State Circuits Conference (ISSCC) in San Francisco late yesterday, Cyclos claims that the x86 processing core design destined for Piledriver processors will include its resonant clock mesh technology.
The technology, invented by Cyclos, uses on-chip inductors to create an electric pendulum known as a 'tank circuit,' formed by the large capacitance of the clock mesh in parallel with the inductors. The result is a system which 'recycles' the clock power instead of watching it dissipate on every clock cycle as with traditional systems.
In other words: it's regenerative braking for processors.
'High-performance processors have used clock mesh designs for years, but with growing emphasis on power reduction in both servers and mobile PCs, the traditional approach has become too power hungry,
' claimed Linley Gwennap, principal analyst of market watcher The Linley Group, in a statement released by Cyclos to coincide with its ISSCC presentation. 'This announcement proves that the Cyclos resonant clock mesh technology provides meaningful power savings in real-world products. We expect other processor designers to adopt the Cyclos technology in applications where power reduction is important.
To back its claims of power savings up, Cyclos has some real-world figures. Based on Piledriver-based x86 processing cores running at 4GHz and above, the resonant clock mesh technology drops clock distribution power by up to 24 per cent at peak and between five and 10 per cent on average in the company's testing. Clock-skew, a serious issue in high-speed processors, is claimed to be unaffected by the drop in power draw.
Those figures are impressive, but a fair way away from the company's ARM926-based test chip created in 2009. On that platform, which ran at 250MHz as a proof of concept, the technology boasted a 25 to 35 per cent drop in power draw depending on the currently running application and its particular needs.
'We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule,
' explained Samuel Naffziger, AMD corporate fellow, of the partnership. 'Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamouring for more energy efficient processor designs.
AMD has confirmed that Cyclos' resonant clock mesh technology will be a part of the x86 portions of Piledriver on the desktop and in the server room. Cyclos itself, meanwhile, has announced plans to target system-on-chip (SoC) companies like Texas Instruments, Nvidia, Qualcomm and Intel with the same technology in order to drive down the power draw of mobile processors.
If you're wondering just how the resonant clock mesh technology works, there's a great write-up over on SemiWiki