AMD announces 32-core eight-RAM-channel Naples family

March 8, 2017 | 10:54

Tags: #ddr4 #naples #ryzen #server #soc #system-on-chip #zen

Companies: #amd

AMD has formally confirmed its Naples server-oriented Zen architecture processor, designed for those with need of wider threading support than the consumer-oriented Ryzen family, will offer 32 cores and 64 threads with support for up to two processors per board.

Details of the Zen-based Naples chips have been leaking out for some considerable time, but AMD has now officially gone on the record: Naples will launch later this year with the top-end model offering 32 physical processing cores with support for 64 simultaneous threads. As per the previous rumours, Naples isn't a simple processor but a system-on-chip (SoC) design with on-board support for 64 lanes of PCI Express 3.0 connectivity, AMD's Infinity Fabric high-performance coherent interconnect for dual-processor implementations, and eight-channel memory - the latter allowing for up to 32 DDR4 DIMMs in a single server across 16 memory channels and supporting a theoretical maximum memory capacity of 4TB.

'Today marks the first major milestone in AMD re-asserting its position as an innovator in the datacentre and returning choice to customers in high-performance server CPUs,' crowed AMD's Forrest Norrod at the unveiling. ''Naples' represents a completely new approach to supporting the massive processing requirements of the modern datacentre. This groundbreaking system-on-chip delivers the unique high-performance features required to address highly virtualised environments, massive data sets and new, emerging workloads.'

AMD has said that it will launch Naples formally in the second half of this year, though has not yet providing pricing information; neither has the company announced partner companies which are planning to launch server products based around Naples, a market currently dominated by Intel's Xeon family of processors. More information is available on AMD's announcement page, while the announcement presentation for the chips is reproduced below.

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