Staying on the GPU die for a moment, Turing implements 32-bit memory controllers (up to 12 on TU102, up to eight on TU104/TU106), and each of these is tied to a partition of eight ROPs and a slice of L2 cache. So far, so Pascal, but this segment of L2 has doubled from 256KB to 512KB, meaning L2 cache levels of 6MB or 4MB depending on GPU. The bandwidth for L2 cache is also said to be ‘significantly higher’, and having more/faster L2 is obviously a recipe for success. However, with today’s massively detailed textures, plenty of data is still going to be stored off-die, and that’s where GDDR6 comes into play.

GDDR6 is the next major iteration of GDDR, supplanting the mid-step GDDR5X, and Turing is the first GPU architecture to implement it. The primary benefit of GDDR6 is raw speed; whereas the GTX 1080 Ti had memory clocked at 11Gbps, all three GeForce RTX cards will have GDDR6 memory with an effective bandwidth of 14Gbps. Such rapid data transfer required a full redesign of the interface circuits and end-to-end optimisation of the entire signal path, with the eventual result being a claimed 40 percent reduction in crosstalk. We’re also told efficiency is up 20 percent over GDDR5X, with Nvidia having used extensive clock gating to reign in power consumption during low utilisation periods.

Compression is the third piece of the memory pie. Lossless compression techniques are nothing new, and the benefits of reducing the footprint of data throughout the GPU’s memory structures without losing anything on the output should be obvious. Without specifying the exact techniques and only saying that they build on those from the Pascal architecture, Nvidia claims to have achieved an effective memory bandwidth improvement of around 50 percent between the GTX 1080 Ti and RTX 2080 Ti, despite the raw memory bandwidth “only” having improved by 27 percent (i.e. 11Gbps to 14Gbps on the same 352-bit interface). How the rest of that figure is portioned between internal cache improvements and compression algorithm tweaks is unknown.


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