October 9, 2017 // 10:26 a.m.
Researchers have come up with a technique for solving a serious bottleneck in the performance of solid-state RAID arrays: Layout-Aware Write Cache (LAWC), which is claimed to boost response time by up to 82 percent compared to current state-of-the-art write cache systems.
Although solid state storage has been around for many decades, the inexorable march of Moore's Law has seen to it that today's flash memory devices have become capacious enough for mass storage. Combined in arrays of multiple devices - RAID, for Redundant Array of Independent Disks - solid state drives can be found acting as high-speed storage for top-end high-performance computers (HPCs) and data centre systems. Researchers from the University of Texas at San Antonio, though, claim both that there's a serious bottleneck hampering performance of such systems and that they have developed the cure: Layout-Aware Write Cache (LAWC).
'The variations in latency and throughput occurring due to uncoordinated internal garbage collection cripples further boosting of performance. In addition, the unwanted variations in each SSD can influence the overall performance of the entire flash storage adversely,' the abstract for a paper written by researchers Kalidas Ganesh, Youngjae Kim, Monobrata Debnath, Sungyong Park, and Junghee Lee and published in the journal IEEE Transactions on Computers Volume 66 claims. The solution: a new type of write caching system which takes into account the characteristics of solid state devices. The LAWC design, the team's paper explains, offers three key features: An improved input/output (I/O) scheduler for logically partitioned write caches combines with a write synchronisation mechanism allowing individual write caches to coordinate their cache flushing, while a two-level hybrid cache algorithm using a small front-level cache improves overall efficiency.
Details aside, the team's testing shows considerable promise: A RAID controller based around the LAWC system reduces response times by 82.39 percent in a RAID 0 (striping) array and by 68.51 percent in a RAID 5 (striping with distributed parity), both as measured against a controller running a 'state-of-the-art write cache algorithm.'
The team's paper, LAWC: Optimising Write Cache Using Layout-Aware I/O Scheduling for All Flash Storage, is available behind a paywall on the IEEE Computer Society website now.