SSE5 instruction set coming in 2009

Author: Phil Cogar
Published: 31st August 2007
Comments (11) Stumble
The x86 architecture will live on with the introduction of SSE5 in 2009.

The x86 architecture will live on with the introduction of SSE5 in 2009.

Yesterday, AMD announced its plans to help improve the performance of applications on the x86 architecture with the introduction of SSE5 instructions.

SSE5 is designed to help software developers to simplify code and improve efficiency by giving them even more capabilities to maximize the performance of applications. The instruction set is currently being made available but will not debut in a chipset until 2009 when AMD releases its "Bulldozer" core for the Fusion line of processors.

The key components of SSE5 include:
  • 3-Operand Instructions - A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.

  • Fused Multiply Accumulate - The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.
For those of you who are interested, you can get a copy of the SSE5 specification over at AMD's developer site. Go ahead and take a peak and let us know what you think about it in the comments section below or over in the forums.


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SSE5 instruction set coming in 2009

AMD hopes to increase the performance of future x86 based processors with the introduction of SSE5 on its "Bulldozer" line of CPU cores in 2009.

http://www.bit-tech.net/news/2007/08/31/sse5_instruction_set_coming_in_09/1


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