The Secrets of PC Memory: Part 1
| Features | Unit | DDR1 | DDR2 | DDR3 |
| Connecting Pins | ||||
| DIMM | 184 | 240 | 240 | |
| SO-DIMM | 100 200 | 200 | 204 | |
| Registered DIMM | 184 | 240 | 240 | |
| Mini-DIMM | - | 244 | - | |
| Micro-DIMM | 172 | 214 | - | |
| Packaging | 60-pin TSOP2 / 60-pin FBGA / LQFP | 60/84-pin FBGA | 78/96-pin FGBA / FBGA with Mirroring | |
| Length | mm | |||
| DIMM | 133.35 (5.25) | 133.35 (5.25) | 133.35 (5.25) | |
| SO-DIMM | 66.7 (2.625) | 66.7 (2.625) | 66.7 (2.625) | |
| Registered DIMM | 133.35 (6.25) | 133.35 (6.25) | 133.35 (6.25) | |
| Mini-DIMM | - | 82 (3.23) | 83 (3.23) | |
| Micro-DIMM | 54 (2.13) | 54 (2.13) | 54 (2.13) | |
| Dram Core Freq | MHz | 100 - 200 | 100 - 200 | 100 - 200 |
| Topology | Asymmetric T-Branch (T-Daisy) | Symmetric T-Branch | Fly-By with Termination | |
| JEDEC Classified Data Rate | DDR-200/266/333/400 | DDR2-400/533/667/800 | DDR3-800/1066/1333/1600 | |
| Prefetch Width | bits | 2 | 4 | 8 |
| Bandwidth (theoretical) | GB/s | |||
| Single-Channel | 1.6 / 2.13 / 2.67 / 3.2 | 3.2 / 4.26 / 5.34 / 6.4 | 6.4 / 8.53 / 10.67 / 12.8 | |
| Dual-Channel | 2.2 / 4.26 / 5.32 / 6.4 | 6.4 / 8.52 / 10.68 / 12.8 | 12.8 / 17.06 / 21.34 / 25.6 | |
| Module Capacity | 128MB - 1GB | 256MB - 4GB (8GB) | 512MB - 8GB (16GB) | |
| Number of Banks | 4 | 4 or 8 | 8 | |
| Read/Write Leveling | No | No | Yes | |
| Supply Voltage | Volts | 2.5 +/- 0.2 | 1.8 +/- 0.1 | 1.5 +/- 0.075 |
| Max Operating Temp | ºC (ºF) | 85 (185) | 85 (185) | 85 (185) |
| I/O Width | x4 / x8 / x16 | x4 / x8 / x16 | x4 / x8 / x16 / x32 | |
| DIMM Calibration Resistors | No | No | Yes | |
| Burst Length | 2, 4 | 4, 8 | 4 (Burst Chop), 8 | |
| RHoS | Vendor Dependent | Vendor Dependent | Vendor Dependent | |
| Latency | ||||
| CAS Latency (CL) | tCK | 2, 2.5, 3 | (2), 3, 4, 5, 6 | 5, 6, 7, 8, 9, 10, (11) |
| Additive Latency (AL) | tCK | - | 0, 1, 2, 3, 4 | 0, 1, 2 |
| READ Latency (RL) | tCK | CL | CL+AL | CL+AL |
| WRITE Latency (WL) | tCK | 1 | RL-1 | 5, 6, 7, 8 |
| CAS Write Latency (CWL) | tCK | - | - | 5, 6, 7 |
| DQ Timing | ||||
| READ | DLL aligns DQ, DQS to CK | DLL aligns DQ, DQS, DQSb, RDQS to CK | DLL aligns DQ, DQS, DQSb to CK | |
| WRITE | Setup / Hold to DQS | Setup / Hold to DQS DQSb | Setup / Hold to DQS DQSb | |
| Data Strobes | Single-ended data strobe | Single-ended or Differential data strobe | Differential data strobe with WRITE leveling | |
| Termination | Motherboard Chipset | On-Die Termination | Dynamic On-Die | |
| Driver Calibration | No | Off-Chip Driver (OCD) | On-Chip Self-Calibration with ZQ pin | |
| DQ Driver Strength | Narrow Envelope | 18 +/-3 Ohms, OCD Calibration | 30-40 Ohms, ZQ pin Calibration | |
| Interrupts | Yes | Wr-Wr, Rd-Rd (4n only) | Burst Chop for Rd and Wr | |
| Reset Function | No | No | Yes (Asynchronous) | |
| Thermal Sensor | No | SO-DIMM (on DIMM), FB-DIMM (on Die) | SO-DIMM (on DIMM), FB-DIMM (on Die) | |
| Automatic Self Refresh (ASR) | Supported | Supported | Supported | |
| Temp. Compensated Self Refresh (TCSR) | Supported | Supported | Supported | |
| Self Refresh Temp (SRT) | <= 85 ºC | <= 95 ºC | <= 85 ºC, <= 95 ºC | |
| Partial Array Self Refresh (PASR) | Supported | Supported | Supported | |
| Deep Power Down (DPD) | Supported | Supported | Supported | |
| Clock Stop Mode | Supported | Supported | Supported |
Data Sources: JEDEC, Altera Corporation, Elpida Memory, Infineon Technologies, Kingston Technology, Micron Technology, MOSAID Technologies, Qimonda, Rambus, Samsung Semiconductor, Via Technology
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