Published on 19th March 2008 by
Tim Smalley & Richard Swinburne
Originally Posted by dmakjust a question, AMD brought out phemon a while ago right? then why are we hearing about a release coming up? is it some sort of rerelease that will fix the problems with the current architecture? like being able to scale past 3 ghz?
Originally Posted by dmakcool thanks, the b3's are 3 cores though arent they? are there quads with this fix as well?
Originally Posted by Nehalem page By being inclusive this means there is automatically an amount of cache reserved in L3 to hold L2 and L1 data, so that none of the cores have to waste cycles sniffing another core’s cache for information – now it just has to simply dive into the shared L3 cache. Intel says that the first Nehalem-based product will be quad-core and will feature 8MB of L3 cache, which means that around 2,256KB of L3 cache will be reserved for a copy of the L1 and L2 caches on each core.
This does cut the available size for everything else to about 6MB and this is quite a drop from the current 2x6MB shared cache design on current quad-core 45nm parts.
Originally Posted by Slinkpeta flops ey?
Originally Posted by CupboardWhy a 3 channel DDR3 controller? Does that mean we will get motherboards with support for up to 6 memory slots?
Originally Posted by CupboardLarrabee sounds interesting though I can't see them killing Nvidia for some time (AMD/ATI may be a different matter though)
You are not logged in, please login with your forum account below. If you don't already have an account please register to start contributing.
27th June 2016
23rd June 2016
21st June 2016
© Copyright bit-tech