Rumour control: Why Larrabee will be based on P54C

Posted at: 4:10pm 9th July 2008 by Ben Hardwidge

After giving P54C to the American military, Intel apparently now has the core back, and it’s been thoroughly debugged with a much smaller footprint

As you may have noticed, we recently updated a Rumour Control story about Larrabee being based on several P54C (original Pentium) cores after a response from Intel. Interestingly, however, Intel didn’t deny the rumour, but simply pointed out that it was German tech site Heise who suggested that Larrabee would be based on P54C, rather than Pat Gelsinger. Interestingly, though, another tech site, Ars Technica, claims to know that Larrabee will indeed be based on P54C.

The site claims that it’s been ‘sitting on’ the same information since last year, and reiterates that ‘Larrabee is, in essence, a bunch of P54C (i.e. pre-MMX) Pentium cores that have been enhanced with very wide vector floating-point resources.’ What’s more interesting, though, is the reason why.

According to Ars Technica, when the old P54C core was past its prime, Intel gave the core’s RTL code to the Pentagon so that the American military could develop a ‘radiation hardened’ version for military applications. Apparently, the Pentagon, which has its own facilities for chip fabrication, then worked on cleaning up the core’s RTL code, before offering it back to Intel when it was no longer useful. After the work from the Pentagon, Ars Technica claims that the P54C now ‘has a very small footprint, and has also been ‘pretty thoroughly debugged.’

Intel has now ‘modified it for use in the many-core chip that later became Larrabee,’ says the site. Of course, this is all still very much a rumour, but Heise’s speculation could well be on the ball. Larrabee is due to be shown at Siggraph later this year, and Intel has already revealed a few details here. According to the Siggraph write-up, ‘Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit,’ which could well mean multiple P54C (also an in-order x86 architecture) cores with a 512-bit wide SIMD (single instruction, multiple data) vector processing unit, as suggested in our original story.

The Siggraph write-up continues, saying that Larrabee ‘provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads and greatly increases the flexibility and programmability of the architecture as compared to standard GPUs.’