Core i7 New Design

Core i7 has received a few upgrades over its Core 2 predecessors

NEW PROCESSOR DESIGN

Confusingly, although Intel still refers to the Core i7 architecture as Core, the same name as that of earlier Core 2 CPUs, the architecture has undergone a massive overhaul. The primary objective of the architects was to increase performance without increasing power consumption. This entailed devising ways to boost performance other than simply adding more cores, extending the pipeline or increasing the clock frequency.

This objective was achieved using two main methods: firstly, improving existing features from the Core architecture; and secondly, by adding new features. For example, Intel has added massively improved the amount of micro-ops that can be processed per clock, as well is increasing their potential complexity. A Core i7 processing core can process up to 128 micro-ops simultaneously while a Core 2 processing core can only handle up to 96. This makes a Core i7 more efficient at handling a range of tasks than previous designs.

As well as adding SSE4.2 instructions to the x86 instruction set of Core i7, Intel has also revised and updated its Penryn 45nm manufacturing process to improve power efficiency. These tweaks, revisions and redesigns underpin the huge performance leap of Core i7 over previous processors, while keeping its power consumption similar to a Core 2 Quad.

BAGS OF CACHE

As each processor core is now fully independent, the cache architecture has had to be completely redesigned. While Core i7 processors retain the same basic Level 1 cache architecture of previous Core 2 designs, each processing core has its own 256KB of Level 2 cache.

This is much less than the 2-6MB that pairs of Core 2 processing cores share. However, Core i7 processors have 8MB of Level 3 cache for all four processing cores to share, something previously only seen on very high-end Xeon MP CPUs.

The Level 3 cache of Core i7 is described as inclusive, which means that it holds the data of all the Level 2 caches. This means that if a core needs to fetch data, and it doesn’t find it in the Level 3 cache, it can be confident that the most up-to-date version of that data is held in the system memory and collect it straight from there.

If the Level 3 cache weren’t inclusive, the core would first have to look at the cache of the other three cores to ensure that none of these had a more recent version of the data it needs. Snooping in these caches could mean stalling these processing cores.

An inclusive cache is therefore said by Intel to be more efficient than an exclusive cache design, even if means that 1MB of the Level 3 cache is always used by storing a copy of the 256KB Level 2 caches inside each of the four processing cores.

NEW HYPER-THREADING

Core i7 also sees the return of Hyper-Threading, last seen in the dual-core Pentium Extreme Edition 965 in late 2006. This technology works in the same way as it did with the Pentium 4, using the spare resources of an execution unit to run a second thread in parallel.