Intel Core i7 and X58 revealed

Posted at: Wednesday 27th August 2008 by Clive Webster

Everything you need to know about Intel's next-generation Nehalem CPUs and X58 chipset, including hints about how it will overclock

Note: This is a preview article, now that Core i7 has launched, please click here for the Core i7 launch coverage.

After Intel revealed more details about Nehalem to CPC at IDF Fall 2008, we’re finally in a position to tell you almost everything there is to know about the new Core i7 processor, which was, until recently, better known by its codename, Nehalem. After days of lengthy briefings we’ve discovered its new design, new features, new technology and even some of its benchmarking and overclocking characteristics.

We’ll cover the basics in this section – what Nehalem is and why it’s such a sweeping change for Intel. Scroll to the bottom of the page to skip to read more in-depth discussions of specific aspects of the new CPUs that will form the basis of Intel's high-performance product line over the next few years.

NEHALEM - NATIVE AND INCLUSIVE

Nehalem is a radically new design for Intel: for the first time, the company is producing a 'native' quad-core CPU, where all four cores sit on the same piece of silicon. With its Core 2 CPUs, Intel used two dual-Core dies to create a quad-core chip.

Nehalem features Level 3 cache, something first seen on earlier Xeon server chips, but Intel has indicated its Core i7s will feature up to a massive 8MB (shared between all four cores) rather than the 2MB of the Phenom X4. Each of Nehalem's four cores has 256KB of lower-latency Level 2 cache rather than the 512KB of the Phenom X4.

The Level 3 cache of Nehalem is described as being ‘inclusive’, meaning that it holds the data of all the Level 2 caches. This means that if a core needs to fetch data, and it doesn’t find it in the Level 3 cache, it can be confident that the most up-to-date version of that data is held in system memory and fetch straight from there. If the Level 3 cache wasn’t inclusive, the core would first have to look at the cache of the other three cores to ensure that none of them had a more recent version of the data it needs. An inclusive cache is therefore said by Intel to be more efficient than an ‘exclusive’ cache design, even if it does mean that 1MB of Nehalem’s 8MB Level 3 cache is taken up by storing a copy of the 256KB Level 2 cache inside each processing core.

INTEGRATED MEMORY CONTROLLER

Intel has also followed AMD in bringing the memory controller onto the Nehalem CPU die rather than having it be part of the Northbridge on the motherboard. It's achieved this by modularising the design of the CPU. The seperate processing cores and caches are linked to the onboard memory controller via a new bus standard called QuickPath (sometimes called QPI, short for QuickPath Interconnect).

As QuickPath replaces the Frontside Bus (FSB) and Northbridge combo, it also takes over the role of allowing the CPU to connect to other system components, busses and controllers such as the PCI Express controller and DDR3 memory. This will, among other things, allow a Nehalem processor to have an integrated graphics processor, much like AMD’s forthcoming Fusion product. We doubt that Nehalem processors with integrated graphics will show up for at least six months, and Intel has given no roadmap for this.